1. Field of the Invention
The present invention relates to a timing analysis apparatus and method for use in semiconductor integrated circuits and, in particular, to a timing analysis apparatus and method for calculating the delay time of logic gates in a semiconductor large-scale digital integrated circuit (LSI) in consideration of fluctuations in power supply and ground voltages of LSI, i.e., influences of power supply and ground noises.
2. Description of the Related Art
In accordance with developments in the semiconductor manufacturing process, a large amount of logic gate circuit employing submicron transistors are integrated at high density in a digital LSI. Fluctuations in the voltage of the power wiring and ground wiring generated in the operation of such a digital LSI, i.e., the power supply noises are actualized by a reduction in the power supply voltage caused by the scale shrinkage and becomes unignorable. The effective power supply voltage value and the ground voltage value applied to the logic gates during the switching operation needs to be taken into consideration for the calculation of the delay time of the logic gate.
Handling of the power supply noises by the conventional timing analysis method can be considered by being separated into its DC component (IR drop) and temporal fluctuation components (dynamic drop). The former is the DC component of a voltage drop obtained by multiplying an average power current value of a digital LSI by the resistance component of an internal power net and a ground net. In this case, the average power current value can be obtained by, for example, integrating the power current of the entire test vector duration given to a digital LSI and averaging the resultant by the test vector duration.
Moreover, in order to express a voltage fluctuation distribution in the plane of a large-scale digital LSI, it is also performed to obtain the distribution of the effective voltage value by dividing a digital LSI into a mesh or blocks and obtaining the average current value in every small region. In this case, the delay time of logic gates is assumed to fluctuate in proportion to the effective voltage value and calculated as an amount of change from the delay time in the nominal voltage value. On the other hand, the latter includes a technique to statically approximate the dynamic noise every short time interval by averaging a voltage fluctuation value within the operation time of the logic gates (See, for example, Non-Patent Document 1). Updating of the delay time of the logic gate is similar to that of the former. Prior art documents related to the present invention are as follows:    Patent Document 1: U.S. Pat. No. 3,569,681;    Non-Patent Document 1: K. Shimazaki, et al., “An Integrated Timing and Dynamic Supply Noise Verification for Nano-meter CMOS SoC Designs”, Proceedings of IEEE 2005 Custom Integrated Circuits Conference (CICC 2005), pp. 31-34, September 2005;    Non-Patent Document 2: M. Fukazawa et al., “Measurements of Digital Signal Delay Variation Due to Dynamic Power Supply Noise”, Proceedings of IEEE Asian Solid-State Circuits Conference 2005 (A-SSCC 2005), #6-6, pp. 165-168, November 2005; and    Non-Patent Document 3: M. Fukazawa et al., “Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform”, Proceedings of IEEE 2006 Custom Integrated Circuits Conference (CICC 2006), pp. 865-868, September 2006.
It has been known that the voltage fluctuations of the actual power supply and the ground, i.e., noises contain frequency components in a wide band ranging from low-frequency components including a direct current, and ranging to the clock frequency and its higher harmonics of the LSI. In a manner similar to that of the prior art described above, fluctuations in a cycle sufficiently longer than the switching operation time of the logic gates can be approximated as constant power and ground voltages operative on the logic gate.
However, the fluctuation components in a cycle equivalent to or shorter than the switching operation time (i.e., high frequency) are operative as dynamic changes in the effective power supply and ground voltages in the process of the switching operation of the logic gate, and a current change due to this fluctuates the delay time. In this case, the delay time of the logic gates is influenced by a time difference between the timing of the switching operation and the timing of the noise in the time window of gate switching, and this cannot be analyzed by the conventional technique (See, for example, Non-Patent Documents 2 and 3 and FIG. 3).
As described above, the conventional timing analysis method, which does not include the calculation of the delay time in consideration of the temporal fluctuations of the power supply noise and the ground noise, has therefore been unable to obtain sufficient analysis accuracy.